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Friday_Colloquium_CMPS359-002_CSCE595-001 - Shared screen with speaker view
Mohsen
51:08
Thank you Dr Sehatbakhsh. Is your simulator based on some measurement also from ASIC design or it's based on some models?
prasanna.kawatkar
51:55
Are you considering the effect of noise signal in your Model ?
Mohsen
56:16
The physical size of ASIC ICs and implementation on FPGAs are tiny. How do you measure each RISC processor pipeline (IF ID EX and... ) stage with an oscilloscope and ordinary handhold probe? How you can filter other side-channel signals noise in the environment when you measure the RISC processor signals with oscilloscope?